Hardware Description Languages for FPGA Design

Level:All Levels
InstructorTimothy Scherr
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Course description
This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.
Meet your instructors:
Timothy Scherr photo
Timothy Scherr
Senior Instructor and Professor of Engineering Practice
Benjamin Spriggs photo
Benjamin Spriggs
Lecturer and Scholar of Engineering Practice